Fonte: Wikipedia
{Electronic design, Digital electronics, Computer hardware, Electronic engineering}
A
And-inverter graph
Antenna effect
Asia and South Pacific Design Automation Conference
Asynchronous systems
Automatic test pattern generation
B
Black's equation
Boolean satisfiability problem
C
Channel router
Circuit extraction
Clock Domain Crossing Verification
Clock distribution network
Clock gating
Composability
Configware
D
DIME-C
Delay calculation
Design Automation Conference
Design Automation and Test in Europe
Design For Test
Design closure
Design flow (EDA)
Design for manufacturability (IC)
Design rule checking
Digital electronics
E
EDA database
Electromagnetic field solver
Electromigration
Electronic Design Magazine
Electronic design automation
Electronic system level
Elmore delay
Emulation for Logic Validation
Espresso heuristic logic minimizer
F
Fault coverage
Field-programmable gate array
Floorplan (integrated circuits)
Floorplanning
Flowware
Formal equivalence checking
Formal verification
Functional verification
G
GDSII
GEDA
Generic array logic
H
Hardware emulation
I
IC layout editor
International Conference on Computer-Aided Design
International Symposium on Physical Design
International Symposium on Quality Electronic Design
L
Ladder logic
Layout Versus Schematic
Logic optimization
Logic simulation
Logic synthesis
M
Mask data preparation
Mitrionics
Morphware
Multi Project Chip
N
Nallatech
Netlist
Network On Chip
Noise margin
O
OpenFire Soft Processor
Optical proximity correction
P
Parasitic Extraction
Physical timing closure
Physical verification
Place and route
Placement (EDA)
Potential applications of carbon nanotubes
Power network design (IC)
Power optimization (EDA)
Programmable Array Logic
Programmable logic array
Programmable system device
R
Register transfer level
Rent's Rule
Resolution enhancement technologies
Retiming
Routing (EDA)
S
Satisfiability Modulo Theories
Scan chain
Schematic
Schematic capture
Semiconductor device modeling
Semiconductor intellectual property core
Semiconductor process simulation
Semulation
Signal integrity
Standard cell
State logic
Static timing analysis
Statistical static timing analysis
Stuck-at fault
Substrate coupling
Systems design
T
Technology CAD
Timing Closure
Transaction-level modeling
V
Value change dump
